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19-2037; Rev 0; 5/01
14-Bit ADC, 200ksps, +5V Single-Supply with Reference
General Description
The MAX1142/MAX1143 are 200ksps, 14-bit ADCs. These serially interfaced ADCs connect directly to SPITM, QSPITM, and MICROWIRETM devices without external logic. They combine an input scaling network, internal track/hold, a clock, +4.096V reference, and three general-purpose digital output pins (for external multiplexer or PGA control) in a 20-pin SSOP package. The excellent dynamic performance (SINAD 81dB), high-speed (200ksps), and low power (7.5mA) of these ADCs, make them ideal for applications such as industrial process control, instrumentation, and medical applications. The MAX1142 accepts input signals of 0 to +12V (unipolar) or 12V (bipolar), while the MAX1143 accepts input signals of 0 to +4.096V (unipolar) or 4.096V (bipolar). Operating from a single +4.75V to +5.25V analog supply and a +4.75V to +5.25V digital supply, power-down modes reduce current consumption to 1mA at 10ksps and further reduce supply current to less than 20A at slower data rates. A serial strobe output (SSTRB) allows direct connection to the TMS320-family of digital signal processors. The MAX1142/MAX1143 user can select either the internal clock, or an external serial-interface clock for the ADC to perform analog-to-digital conversions. The MAX1142/MAX1143 feature internal calibration circuitry to correct linearity and offset errors. On-demand calibration allows the user to optimize performance. Three user-programmable logic outputs are provided for the control of an 8-channel MUX or a PGA.
Features
o 200ksps (Bipolar) and 150ksps (Unipolar) Sampling ADC o 14-Bits, No Missing Codes o 1LSB INL Guaranteed o 81dB (min) SINAD o +5V Single-Supply Operation o Low Power Operation, 7.5mA (Unipolar Mode) o 2.5A Shutdown Mode o Software-Configurable Unipolar & Bipolar Input Ranges 0 to +12V and 12V (MAX1142) 0 to +4.096V and 4.096V (MAX1143) Internal or External Reference o Internal or External Clock o SPI/QSPI/MICROWIRE-Compatible Wire Serial Interface o Three User-Programmable Logic Outputs o Small 20-Pin SSOP Package
MAX1142/MAX1143
Ordering Information
PART MAX1142ACAP TEMP. RANGE 0C to +70C 0C to +70C PINPACKAGE 20 SSOP 20 SSOP INL (LSB) 1 2
Applications
Industrial Process Control Industrial I/O Modules Data-Acquisition Systems Medical Instruments Portable and Battery-Powered Equipment
MAX1142BCAP
Ordering Information continued at end of data sheet.
Pin Configuration
TOP VIEW
REF 1 REFADJ 2 AGND 3 AVDD 4 DGND 5 SHDN 6 20 AIN 19 AGND 18 CREF 17 CS
MAX1142 MAX1143
16 DIN 15 DVDD 14 DGND 13 SCLK 12 RST 11 DOUT
Functional Diagram appears at end of data sheet. Typical Application Circuit appears at end of data sheet. SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
P2 7 P1 8 P0 9 SSTRB 10
SSOP
________________________________________________________________ Maxim Integrated Products
1
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14-Bit ADC, 200ksps, +5V Single-Supply with Reference MAX1142/MAX1143
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND, DVDD to DGND .............................-0.3V to +6V AGND to DGND.....................................................-0.3V to +0.3V AIN to AGND.....................................................................16.5V REFADJ, CREF, REF to AGND.................-0.3V to (AVDD + 0.3V) Digital Inputs to DGND.............................................-0.3V to +6V Digital Outputs to DGND .........................-0.3V to (DVDD + 0.3V) Continuous Power Dissipation (TA = +70C) 20-SSOP (derate 8.00mW/C above +70C) ...............640mW Operating Temperature Ranges MAX114_CAP ......................................................0C to +70C MAX114_EAP....................................................-40C to +85C Storage Temperature Range .............................-60C to +150C Junction Temperature ......................................................+150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD = DVDD = +5V 5%, fSCLK = 4.8MHz, external clock (50% duty cycle), 24 clocks/conversion (200ksps), bipolar input, external VREF = +4.096V, VREFADJ = AVDD, CREF = 2.2F, CCREF = 1F, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER DC ACCURACY (Note 1) Resolution Relative Accuracy (Note 2) Differential Nonlinearity Transition Noise Offset Error Gain Error (Note 3) Offset Drift (Bipolar and Unipolar) Gain Drift (Bipolar and Unipolar) Unipolar Bipolar Unipolar Bipolar Excluding reference drift Excluding reference drift 1 1 INL DNL Unipolar Mode MAX114_A MAX114_B Unipolar Mode 0.34 4 6 0.2 0.3 14 1 2 1 Bits LSB LSB LSB RMS mV %FSR ppm/oC ppm/oC SYMBOL CONDITIONS MIN TYP MAX UNITS
DYNAMIC SPECIFICATIONS (5kHz sine-wave input, 200ksps, 4.8MHz clock, bipolar input mode). (MAX1142, 24Vp-p. MAX1143, 8.192Vp-p) SINAD SNR THD SFDR ANALOG INPUT MAX1142 Input Range MAX1143 Unipolar Bipolar Unipolar Bipolar 0 -12 0 -4.096 12 12 4.096 4.096 V fIN = 5kHz fIN = 100kHz fIN = 5kHz fIN = 100kHz fIN = 5kHz fIN = 100kHz fIN = 5kHz fIN = 100kHz 90 95 91 82 82 -88 81 82 dB dB dB dB
2
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14-Bit ADC, 200ksps, +5V Single-Supply with Reference
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = +5V 5%, fSCLK = 4.8MHz, external clock (50% duty cycle), 24 clocks/conversion (200ksps), bipolar input, external VREF = +4.096V, VREFADJ = AVDD, CREF = 2.2F, CCREF = 1F, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER SYMBOL MAX1142 Input Impedance MAX1143 Input Capacitance CONVERSION RATE Internal Clock Frequency Aperture Delay Aperture Jitter tAD tAJ Unipolar Bipolar Unipolar Bipolar Unipolar Bipolar 0.1 0.1 4.17 4.17 8 5 4 10 50 3 4.8 125 200 240 240 MHz ns ps CONDITIONS Unipolar Bipolar Unipolar Bipolar MIN 7.5 5.9 100 3.4 TYP 10.0 7.9 1000 4.5 32 pF k MAX UNITS
MAX1142/MAX1143
MODE 1 (24 External Clock Cycles per Conversion) External Clock Frequency Sample Rate Conversion Time (Note 4) MODE 2 (Internal Clock Mode) External Clock Frequency (Data Transfer Only) Conversion Time Acquisition Time SSTRB Low Pulse Width Unipolar Bipolar fSCLK fS = fSCLK /32 tCONV+ACQ = 32 / fSCLK VREF Unipolar or Bipolar Unipolar or Bipolar Unipolar or Bipolar 1.82 1.14 0.1 3.125 6.67 4.8 150 320 4 8 6 MHz s s fSCLK fS = fSCLK /24 tCONV+ACQ = 24 / fSCLK MHz ksps s
MODE 3 (32 External Clock Cycles per Conversion) External Clock Frequency Sample Rate Conversion Time (Note 4) INTERNAL REFERENCE Output Voltage REF Short Circuit Current Output Tempco Capacitive Bypass at REF Maximum Capacitive Bypass at REFADJ REFADJ Output Voltage REFADJ Input Range For small adjustments from 4.096V 0.47 10 4.096 100 4.056 4.096 24 20 10 4.136 V mA ppm/oC F F V mV MHz ksps s
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14-Bit ADC, 200ksps, +5V Single-Supply with Reference MAX1142/MAX1143
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = +5V 5%, fSCLK = 4.8MHz, external clock (50% duty cycle), 24 clocks/conversion (200ksps), bipolar input, external VREF = +4.096V, VREFADJ = AVDD, CREF = 2.2F, CCREF = 1F, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER REFADJ Buffer Disable Threshold Buffer Voltage Gain EXTERNAL REFERENCE (Reference buffer disabled. Reference applied to REF) Input Range (Notes 5 and 6) VREF = 4.096V, fSCLK = 4.8MHz Input Current DIGITAL INPUTS Input High Voltage Input Low Voltage Input Leakage Input Hysteresis Input Capacitance DIGITAL OUTPUTS Output High Voltage Output Low Voltage Three-State Leakage Current Three-State Output Capacitance POWER SUPPLIES Analog Supply (Note 7) Digital Supply (Note 7) Analog Supply Current AVDD DVDD Unipolar Mode IANALOG Bipolar Mode SHDN = 0, or software power-down mode Unipolar or Bipolar Mode SHDN = 0, or software power-down mode AVDD = DVDD = 4.75V to 5.25V, 4.75 4.75 5 5 5 8.5 0.3 2.5 2.2 72 5.25 5.25 8 11 10 3.5 10 V V mA A mA A dB VOH VOL IL ISOURCE = 0.5mA ISINK = 5mA ISINK = 16mA CS = DVDD CS = DVDD 10 DVDD 0.5 0.4 0.8 10 V V A pF VIH VIL IIN VHYST CIN VIN = 0 or DVDD 0.2 10 2.4 0.8 1 V V A V pF VREF = 4.096V, fSCLK = 0 In power-down, fSCLK = 0 3.0 4.096 250 230 0.1 A 4.2 V SYMBOL CONDITIONS To power-down the internal reference MIN AVDD 0.5V 1 TYP MAX AVDD 0.1V UNITS V V/V
Digital Supply Current Power Supply Rejection Ratio (Note 8)
IDIGITAL PSRR
4
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14-Bit ADC, 200ksps, +5V Single-Supply with Reference
TIMING CHARACTERISTICS (Figures 5 and 6)
(AVDD = DVDD = +5V 5%, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER Acquisition Time DIN to SCLK Setup DIN to SCLK Hold SCLK to DOUT Valid CS Fall to DOUT Enable CS Rise to DOUT Disable CS to SCLK Rise Setup CS to SCLK Rise Hold SCLK High Pulse Width SCLK Low Pulse Width SCLK Fall to SSTRB CS Fall to SSTRB Enable CS Rise to SSTRB Disable SSTRB Rise to SCLK Rise RST Pulse Width SYMBOL tACQ tDS tDH tDO tDV tTR tCSS tCSH tCH tCL tSSTRB tSDV tSTR tSCK tRS CLOAD = 50pF CLOAD = 50pF, External clock mode CLOAD = 50pF, External clock mode Internal clock mode 0 208 CLOAD = 50pF CLOAD = 50pF 100 0 80 80 80 80 80 CONDITIONS MIN 1.14 50 0 70 80 80 TYP MAX UNIT s ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MAX1142/MAX1143
5
Note 1: Tested at AVDD = DVDD = +5V, bipolar input mode. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and offset error have been nulled. Note 3: Offset nulled. Note 4: Conversion time is defined as the number of clock cycles multiplied by the clock period, clock has 50% duty cycle. Includes the acquisition time. Note 5: ADC performance is limited by the converter's noise floor, typically 300Vp-p. Note 6 When an external reference has a different voltage than the specified typical value, the full scale of the ADC will scale proportionally. Note 7: Electrical characteristics are guaranteed from AVDD(MIN) = DVDD(MIN) to AVDD(MAX) = DVDD(MAX). For operations beyond this range, see the Typical Operating Characteristics. For guaranteed specifications beyond the limits, contact the factory. Note 8: Defined as the change in positive full-scale caused by a 5% variation in the nominal supply voltage.
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14-Bit ADC, 200ksps, +5V Single-Supply with Reference MAX1142/MAX1143
Typical Operating Characteristics
(MAX1142/MAX1143, AVDD = DVDD = +5V , fSCLK = 4.8MHz, external clock (50% duty cycle), 24-clocks/conversion (200ksps), bipolar input, external REF = +4.096V, 0.22F bypassing on REFADJ, 2.2F on REF, 1F on CREF, TA = 25C, unless otherwise noted.)
INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE
MAX1142 toc01
DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE
MAX1142 toc02
TOTAL SUPPLY CURRENT vs. TEMPERATURE
11.3 TOTAL SUPPLY CURRENT (mA) 11.1 10.9 10.7 10.5 10.3 10.1 9.9 9.7 A B C A: AVDD, DVDD = +4.75V B: AVDD, DVDD = +5.00V C: AVDD, DVDD = +5.25V
MAX1142/3 toc03
1.0 0.8 INTEGRAL NONLINEARITY (LSB) 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 1 1717 3433 5149 6865
1.0 DIFFERENTIAL NONLINEARITY (LSB)
11.5
0.5
0
-0.5
-1.0 10297 13729 8581 12013 15445 1 1632 3263 4894 6525 9787 13049 1631 8156 11418 14680
9.5 -40 -20 0 20 40 60 80 TEMPERATURE (C)
DIGITAL OUTPUT CODE
DIGITAL OUTPUT CODE
OFFSET VOLTAGE vs. TEMPERATURE
MAX1142/3 toc04
GAIN ERROR vs. TEMPERATURE
MAX1142/3 toc05
TOTAL SUPPLY CURRENT vs. CONVERSION RATE (USING SHUTDOWN)
MAX1142/3 toc06
0
OFFSET VOLTAGE (V)
-1
0.03 C 0.02 B 0.01
TOTAL SUPPLY CURRENT (mA)
GAIN ERROR (% FULL SCALE)
A: AVDD, DVDD = +4.75V B: AVDD, DVDD = +5.00V C: AVDD, DVDD = +5.25V
0.04
A: AVDD, DVDD = +4.75V B: AVDD, DVDD = +5.00V C: AVDD, DVDD = +5.25V
100
10
-2
B
1
-3
C A
A
0.1
-4 -40 -20 0 20 40 60 80 TEMPERATURE (C)
0 -40 -20 0 20 40 60 80 TEMPERATURE (C)
0.01 0 1 10 100 1000 CONVERSION RATE (ksps)
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14-Bit ADC, 200ksps, +5V Single-Supply with Reference
Typical Operating Characteristics (continued)
(MAX1142/MAX1143, AVDD = DVDD = +5V , fSCLK = 4.8MHz, external clock (50% duty cycle), 24-clocks/conversion (200ksps), bipolar input, external REF = +4.096V, 0.22F bypassing on REFADJ, 2.2F on REF, 1F on CREF, TA = 25C, unless otherwise noted.)
NORMALIZED REF VOLTAGE vs. TEMPERATURE
MAX1142/3 toc07
MAX1142/MAX1143
FFT PLOT
fSAMPLE = 200kHz fIN = 5kHz
MAX1142/3 toc08
SINAD PLOT
90 80 AMPLITUDE (dB) 70 60 50 40 30 20 10 fSAMPLE = 200kHz
MAX1142/3 toc09
1.010
0 -20 AMPLITUDE (dB) -40 -60 -80 -110
100
NORMALIZED REF VOLTAGE
1.005
1
0.995
0.990 -40 -20 0 20 40 60 80 TEMPERATURE (C)
-120 0 9 18 27 36 45 54 63 72 81 90 99 FREQUENCY (kHz)
0 0.1 1 10 100 FREQUENCY (kHz)
SFDR PLOT
MAX1142/3 toc10
THD PLOT
-10 -20 -30 AMPLITUDE (dB) -40 -50 -60 -70 -80 -90 -100 -110 fSAMPLE = 200kHz
MAX1142/3 toc11
120 110 100 AMPLITUDE (dB) 90 80 70 60 50 40 30 20 10 0 0.1 1
0
fSAMPLE = 200kHz
10
100
0.1
1
10
100
FREQUENCY (kHz)
FREQUENCY (kHz)
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14-Bit ADC, 200ksps, +5V Single-Supply with Reference MAX1142/MAX1143
Pin Description
PIN NAME FUNCTION Reference Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion. In internal reference mode, the reference buffer provides a +4.096V nominal output, externally adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling REFADJ to AVDD. Bypass to AGND with a 2.2F capacitor when using the internal reference. Bandgap Reference Output/Bandgap Reference Buffer Input. Bypass to AGND with 0.22F. When using an external reference, connect REFADJ to AVDD to disable the internal bandgap reference. Analog Ground. This is the primary analog ground (Star Ground). Analog Supply 5V 5%. Bypass AVDD to AGND (pin 3) with a 0.1F capacitor. Digital Ground Shutdown Control Input. Drive SHDN low to put the ADC in shutdown mode. User-Programmable Output 2 User-Programmable Output 1 User-Programmable Output 0 Serial Strobe Output. In internal clock mode, SSTRB goes low when the ADC begins a conversion and goes high when the conversion is finished. In external clock mode, SSTRB pulses high for one clock period before the MSB decision. It is high impedance when CS is high in external clock mode. Serial Data Output. MSB first, straight binary format for unipolar input, two's complement for bipolar input. Each bit is clocked out of DOUT at the falling edge of SCLK. Reset Input. Drive RST low to put the device in the power-on default mode. See the Power-On Reset section. Serial Data Clock Input. Serial data on DIN is loaded on the rising edge of SCLK, and serial data is updated on DOUT on the falling edge of SCLK. In external clock mode, SCLK sets the conversion speed. Digital Ground. Connect to pin 5. Digital Supply 5V 5%. Bypass DVDD to DGND (pin 14) with a 0.1F capacitor. Serial Data Input. Serial data on DIN is latched on the rising edge of SCLK. Chip Select Input. Drive CS low to enable the serial interface. When CS is high, DOUT is high-impedance. In external clock mode SSTRB is high-impedance when CS is high. Reference Buffer Bypass. Bypass CREF to AGND (pin 3) with 1F. Analog Ground. Connect pin 19 to pin 3. Analog Input
1
REF
2 3 4 5 6 7 8 9
REFADJ AGND AVDD DGND SHDN P2 P1 P0
10
SSTRB
11 12 13 14 15 16 17 18 19 20
DOUT RST SCLK DGND DVDD DIN CS CREF AGND AIN
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14-Bit ADC, 200ksps, +5V Single-Supply with Reference
Detailed Description
The MAX1142/MAX1143 analog-to-digital converters (ADCs) use a successive-approximation technique and input track/hold (T/H) circuitry to convert an analog signal to a 14-bit digital output. The MAX1142/MAX1143 easily interfaces to microprocessors (Ps). The data bits can be read either during the conversion in external clock mode or after the conversion in internal clock mode. In addition to a 14-bit ADC, the MAX1142/MAX1143 include an input scaler, an internal digital microcontroller, calibration circuitry, an internal clock generator, and an internal bandgap reference. The input scaler for the MAX1142 enables conversion of input signals ranging from 0 to +12V (unipolar input) or 12V (bipolar input). The MAX1143 accepts 0 to +4.096V (unipolar input) or 4.096V (bipolar input). Input range selection is software controlled.
BIPOLAR S1 UNIPOLAR R1 2.5k R2 AIN R3 TRACK S2 HOLD TRACK S3 S1 = BIPOLAR/UNIPOLAR S2, S3 = T/H SWITCH R2 = 7.6k (MAX1142) OR 2.5k (MAX1143) R3 = 3.9k (MAX1142) OR INFINITY (MAX1143) HOLD CHOLD 30pF T/H OUT VOLTAGE REFERENCE
MAX1142/MAX1143
Calibration
To minimize linearity, offset, and gain errors, the MAX1142/MAX1143 have on-demand software calibration. Initiate calibration by writing a Control-Byte with bit M1 = 0, and bit M0 = 1 (See Table 1). Select internal or external clock for calibration by setting the INT/EXT bit in the Control-Byte. Calibrate the MAX1142/MAX1143 with the clock used for performing conversions. Offsets resulting from synchronous noise (such as the conversion clock) are canceled by the MAX1142/ MAX1143's calibration circuitry. However, because the magnitude of the offset produced by a synchronous signal depends on the signal's shape, recalibration may be appropriate if the shape or relative timing of the clock or other digital signals change, as might occur if more than one clock signal or frequency is used.
Figure 1. Equivalent Input Circuit
Digital Interface
The digital interface pins consist of SHDN, RST, SSTRB, DOUT, SCLK, DIN and CS. Bringing SHDN low, places the MAX1142/MAX1143 in its 2.5A shutdown mode. A logic low on RST halts the MAX1142/MAX1143 operation and returns the part to its power-on reset state. In external clock mode, SSTRB is low and pulses high for one clock cycle at the start of conversion. In internal clock mode SSTRB goes low at the start of the conversion, and goes high to indicate the conversion is finished. The DIN input accepts Control-Byte data which is clocked in on each rising edge of SCLK. After CS goes low or after a conversion or calibration completes, the first logic "1" clocked-into DIN is interpreted as the START bit, the MSB of the 8-bit Control-Byte. The SCLK input is the serial data transfer clock which clocks data in and out of the MAX1142/MAX1143. SCLK also drives the A/D conversion steps in external clock mode (see Internal and External Clock Modes section). DOUT is the serial output of the conversion result. DOUT is updated on the falling edge of SCLK. DOUT is high-impedance when CS is high. CS must be low for the MAX1142/MAX1143 to accept a Control-Byte. The serial interface is disabled when CS is high.
Input Scaler
The MAX1142/MAX1143 have an input scaler which allows conversion of true bipolar input voltages while operating from a single +5V supply. The input scaler attenuates and shifts the input, as necessary, to map the external input range to the input range of the internal DAC. The MAX1142 analog input range is 0 to +12V (unipolar) or 12V (bipolar). The MAX1143 analog input range is 0 to +4.096V (unipolar) or 4.096V (bipolar). Unipolar and bipolar mode selection is configured with bit 6 of the serial Control-Byte. Figure 1 shows the equivalent input circuit of the MAX1142/MAX1143. The resistor network on the analog input provides 16.5V fault protection. This circuit limits the current going into or out of the pin, to less than 2mA. The overvoltage protection is active, even if the device is in a power-down mode, or if AVDD = 0.
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14-Bit ADC, 200ksps, +5V Single-Supply with Reference MAX1142/MAX1143
User-Programmable Outputs
The MAX1142/MAX1143 have three user-programmable outputs: P0, P1 and P2. The power-on default state for the programmable outputs is zero. These are pushpull CMOS outputs suitable for driving a multiplexer, a PGA, or other signal preconditioning circuitry. The userprogrammable outputs are controlled by bits 0, 1 and 2 of the Control-Byte (Table 2). The user-programmable outputs are set to zero during power-on reset (POR) or when RST goes low. During hardware or software shutdown P0, P1, and P2 are unchanged and remain low-impedance. bit. If a new start bit occurs before the current conversion is complete, the conversion is aborted and a new acquisition is initiated. Table 1 shows the Control-Byte format.
Internal and External Clock Modes
The MAX1142/MAX1143 may use either the external serial clock or the internal clock to perform the successive-approximation conversion. In both clock modes, the external clock shifts data in and out of the MAX1142/MAX1143. Bit 5 (INT/EXT) of the Control-Byte programs the clock mode.
Starting a Conversion
Start a conversion by clocking a Control-Byte into the device's internal shift register. With CS low, each rising edge on SCLK clocks a bit from DIN into the MAX1142/MAX1143's internal shift register. After CS goes low or after a conversion or calibration completes, the first arriving logic "1" is defined as the start bit of the Control-Byte. Until this first start bit arrives, any number of logic "0" bits can be clocked into DIN with no effect. If at any time during acquisition or conversion, CS is brought high and then low again, the part is placed into a state where it can recognize a new start
External Clock In external clock mode, the external clock not only shifts data in and out, but it also drives the A/D conversion steps. In short acquisition mode, SSTRB pulses high for one clock period after the seventh falling edge of SCLK, following the start bit. The MSB of the conversion is available at DOUT on the eighth falling edge of SCLK (Figure 2).
In long acquisition mode, when using the external clock, SSTRB pulses high for one clock period after the fifteenth falling edge of SCLK, following the start bit. The MSB of the conversion is available at DOUT on the sixteenth falling edge of SCLK (Figure 3).
Table 1. Control-Byte Format
BIT7 (MSB) START BIT 7 (MSB) BIT6 UNI/BIP NAME START BIT5 INT/EXT BIT4 M1 BIT3 M0 BIT2 P2 BIT1 P1 BIT0 (LSB) P0
DESCRIPTION The first logic "1" bit, after CS goes low, defines the beginning of the Control-Byte 1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, analog input signals from 0 to +12V (MAX1142) or 0 to VREF (MAX1143) can be converted. In bipolar mode analog input signals from -12V to +12V (MAX1142) or -VREF to +VREF (MAX1143) can be converted. Selects the internal or external conversion clock. 1 = Internal, 0 = External. M1 0 M0 0 1 0 1 MODE 24 External clocks per conversion (short acquisition mode) Start Calibration. Starts internal calibration Software power-down mode 32 External clocks per conversion (long acquisition mode)
6
UNI/BIP
5 4
INT/EXT M1
3
M0
0 1 1
2 1 0(LSB)
P2 P1 P0
These three bits are stored in a port register and output to pins P2-P0 for use in addressing a MUX or PGA. These three bits are updated in the port register simultaneously when a new Control-Byte is written.
10
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14-Bit ADC, 200ksps, +5V Single-Supply with Reference MAX1142/MAX1143
Table 2. User-Programmable Outputs
OUTPUT PIN P2 P1 P0 PROGRAMMED THROUGH CONTROLBYTE Bit 2 Bit 1 Bit 0 POWER-ON OR RST DEFAULT 0 0 0 DESCRIPTION
User programmable outputs follow the state of the Control-Byte's three LSBs, and are updated simultaneously when a new Control-Byte is written. Outputs are push-pull. In hardware and software shutdown, these outputs are unchanged and remain low-impedance.
In external clock mode, SSTRB is high-impedance when CS is high. In external clock mode, CS is normally held low during the entire conversion. If CS goes high during the conversion, SCLK is ignored until CS goes low. This allows external clock mode to be used with 8bit bytes.
The MSB of the conversion is available at DOUT when SSTRB goes high. The subsequent 15 falling edges on SCLK shift the remaining bits out of the internal storage register (Figure 4). CS does not need to be held low once a conversion is started. When internal clock mode is selected, SSTRB does not go into a high-impedance state when CS goes high. Figure 5 shows the SSTRB timing in internal clock mode. In internal clock mode, data can be shifted into the MAX1142/MAX1143 at clock rates up to 4.8MHz, provided that the minimum acquisition time, tACQ, is kept above 1.14s in bipolar mode and 1.82s in unipolar-mode. Data can be clocked out at 8MHz.
Internal Clock In internal clock mode, the MAX1142/MAX1143 generates its own conversion clock. This frees the microprocessor from the burden of running the SAR conversion clock, and allows the conversion results to be read back at the processor's convenience, at any clock rate up to 8MHz. SSTRB goes low at the start of the conversion and goes high when the conversion is complete. SSTRB will be low for a maximum of 6s, during which time SCLK should remain low for best noise performance. An internal register stores data when the conversion is in progress. SCLK clocks the data out of the internal storage register at any time after the conversion is complete.
CS
Output Data
The output data format is straight binary for unipolar conversions and two's complement in bipolar mode. In both modes the MSB is shifted out of the MAX1142/ MAX1143 first.
tACQ SCLK 1 UNI/ START BIP INT/ EXT 4 8 12 15 21 24
M1
M0
P2
P1
P0
DIN SSTRB
DOUT A/D STATE IDLE ACQUISITION
B13 MSB
B12
B11
B10
B9
B8
B7
B2
B1
B0 LSB
X
X
FILLED WITH ZEROS IDLE
CONVERSION
Figure 2. Short Acquisition Mode (24-Clock Cycles) External Clock, Bipolar Mode
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14-Bit ADC, 200ksps, +5V Single-Supply with Reference MAX1142/MAX1143
CS
tACQ SCLK 1 UNI/ START BIP INT/ EXT 4 8 15 19 21 32
M1
M0
P2
P1
P0
DIN SSTRB
DOUT A/D STATE IDLE ACQUISITION
B13 MSB
B12
B11
B2
B1
B0 LSB
X
X
FILLED WITH ZEROS IDLE
CONVERSION
Figure 3. Long Acquisition Mode (32-Clock Cycles) External Clock, Bipolar Mode
CS
tACQ SCLK 1 UNI/ START BIP INT/ EXT 4 8 9 10 21 24
M1
M0
P2
P1
P0
DIN SSTRB
tCONV DOUT B13 MSB B12 B11 B2 B1 B0 LSB X X FILLED WITH ZEROS
Figure 4. Internal Clock Mode Timing, Short Acquisition, Bipolar Mode
CS
tCONV
tCSS tSCK
tCSH
SSTRB t SSTRB SCLK
PO CLOCKED IN
NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.
Figure 5. Internal Clock Mode SSTRB Detailed Timing
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14-Bit ADC, 200ksps, +5V Single-Supply with Reference
Data Framing
The falling edge of CS does NOT start a conversion on the MAX1142/MAX1143. The first logic high clocked into DIN is interpreted as a start bit and defines the first bit of the Control-Byte. A conversion starts on the falling edge of SCLK, after the seventh bit of the Control-Byte (the P1 bit) is clocked into DIN. The start bit is defined as: The first high bit clocked into DIN with CS low, anytime the converter is idle, e.g. after AVDD is applied, or as the first high bit clocked into DIN after CS is pulsed high, then low. OR If a falling edge on CS forces a start bit before the conversion or calibration is complete, then the current operation will be terminated and a new one started. The MAX1142/MAX1143 should be calibrated after power-up or the assertion of reset. Make sure the power supplies and the reference voltage have fully settled prior to initiating the calibration sequence. Initiate calibration by setting M1 = 0 and M0 = 1 in the Control-Byte. In internal clock mode, SSTRB goes low at the beginning of calibration and goes high to signal the end of calibration, approximately 80,000 clock cycles later. In external clock mode, SSTRB goes high at the beginning of calibration and goes low to signal the end of calibration. Calibration should be performed in the same clock mode as will be used for conversions (Figure 6).
MAX1142/MAX1143
Reference
The MAX1142/MAX1143 can be used with an internal or external reference. An external reference can be connected directly at the REF pin or at the REFADJ pin. CREF is an internal reference node and must be bypassed with a 1F capacitor when using either the internal or an external reference.
Applications Information
Power-On Reset
When power is first applied to the MAX1142/MAX1143 or if RST is pulsed low, the internal calibration registers are set to their default values. The user-programmable registers (P0, P1 and P2) are low, and the device is configured for bipolar mode with internal clocking.
Calibration
To compensate the MAX1142/MAX1143 for temperature drift and other variations, they should be periodically calibrated. After any change in ambient temperature more than 10C, the device should be recalibrated. A 100mV change in supply voltage or any change in the reference voltage should be followed by a calibration. Calibration corrects for errors in gain, offset, integral nonlinearity and differential nonlinearity.
Internal Reference When using the MAX1142/MAX1143's internal reference, place a 0.22F ceramic capacitor from REFADJ to AGND and place a 2.2F capacitor from REF to AGND. Fine adjustments can be made to the internal reference voltage by sinking or sourcing current at REFADJ. The input impedance of REFADJ is nominally 9k. The internal reference voltage is adjustable to 1.5% with the circuit of Figure 7.
CS tSDV SSTRB tSTR
tSSTRB
tSSTRB
SCLK
P1 CLOCKED IN
Figure 6. External Clock Mode SSTRB Detailed Timing
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14-Bit ADC, 200ksps, +5V Single-Supply with Reference MAX1142/MAX1143
External reference An external reference can be placed at either the input (REFADJ) or the output (REF) of the MAX1142/ MAX1143's internal buffer amplifier.
When connecting an external reference to REFADJ, the input impedance is typically 9k. Using the buffered REFADJ input makes buffering of the external reference unnecessary. The internal buffer output must be bypassed at REF with a 2.2F capacitor. When connecting an external reference at REF, REFADJ must be connected to AVDD. The input impedance at REF is 16k for DC currents. During conversion, an external reference at REF must deliver 250A DC load current and have an output impedance of 10 or less. If the reference has a higher output impedance or is noisy, bypass it at the REF pin with a 4.7F capacitor.
100k +5V
MAX1142
510k REFADJ
24k
0.22F
Figure 7. MAX1142 Reference-Adjust Circuit
Analog Input
The MAX1142/MAX1143 use a capacitive DAC that provides an inherent track/hold function. Drive AIN with a source impedance less than 10. Any signal conditioning circuitry must settle with 16-bit accuracy in less than 500ns. Limit the input bandwidth to less than half the sampling frequency to eliminate aliasing. The MAX1142/MAX1143 has a complex input impedance which varies from unipolar to bipolar mode (Figure 1).
MAX1143. Unipolar and bipolar mode is programmed with the UNI/BIP bit of the Control-Byte. When using a reference other than the MAX1142/MAX1143's internal +4.096V reference, the full-scale input range will vary accordingly. The full-scale input range depends on the voltage at REF and the sampling mode selected (Tables 3 and 4).
Input Range The analog input range in unipolar mode is 0 to +12V for the MAX1142, and 0 to +4.096V for the MAX1143. In bipolar mode, the analog input can be -12V to +12V for the MAX1142, and -4.096V to +4.096V for the
Input Acquisition and Settling Clocking-in a Control-Byte starts input acquisition. In bipolar mode, the main capacitor array starts acquiring the input as soon as a start bit is recognized. If unipolar mode is selected by the second DIN bit, the part will immediately switch to unipolar sampling mode and acquire a sample. Acquisition can be extended by eight clock cycles by setting M1 = 1, M0 = 1 (long acquisition mode). The sampling instant in short acquisition completes on the falling edge of the sixth clock cycle after the start bit (Figure 2).
Table 3. Unipolar Full Scale and Zero Scale
PART MAX1142 MAX1143 REFERENCE Internal External Internal External ZERO SCALE 0 0 0 0 FULL SCALE +12V +12(VREF/4.096) +4.096V +VREF
Table 4. Bipolar Full Scale, Zero Scale, and Negative Scale
PART MAX1142 MAX1143 REFERENCE Internal External Internal External NEGATIVE FULL SCALE -12V -12(VREF/4.096) -4.096V -VREF ZERO SCALE 0 0 0 0 FULL SCALE +12V +12(VREF/4.096) +4.096V +VREF
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14-Bit ADC, 200ksps, +5V Single-Supply with Reference
Acquisition is 5.5 clock cycles in short acquisition mode and 13.5 clock cycles in long acquisition mode. Short acquisition mode is 24 clock cycles per conversion. Using the external clock to run the conversion process limits unipolar conversion speed to 125ksps instead of 200ksps in bipolar mode. The input resistance in unipolar mode is larger than that of bipolar mode (Figure1). The RC time constant in unipolar mode is larger than that of bipolar mode, reducing the maximum conversion rate in 24 external clock mode. Long acquisition mode with external clock allows both unipolar and bipolar sampling of 150ksps (4.8MHz/32 clock cycles) by adding eight extra clock cycles to the conversion. Most applications require an input buffer amplifier. If the input signal is multiplexed, the input channel should be switched immediately after acquision, rather than near the end of or after a conversion. This allows more time for the input buffer amplifier to respond to a large step change in input signal. The input amplifier must have a high enough slew-rate to complete the required output voltage change before the beginning of the acquisition time. At the beginning of acquisition, the capacitive DAC is connected to the amplifier output, causing some output disturbance. Ensure that the sampled voltage has settled to within the required limits before the end of the acquisition time. If the frequency of interest is low, AIN can be bypassed with a large enough capacitor to charge the capacitive DAC with very little change in voltage. However, for AC use, AIN must be driven by a wideband buffer (at least 10MHz), which must be stable with the DAC's capacitive load (in parallel with any AIN bypass capacitor used) and also settle quickly (Figures 8 or 9).
1k +15V
MAX1142/MAX1143
510 +5V
0.1F 2 7 6 3 22 AIN 4 0.1F -5V 0.1F
MAX410
IN
Figure 9. 5V Buffer for AC/DC Use has 3.5V Swing
Digital Noise Digital noise can couple to AIN and REF. The conversion clock (SCLK) and other digital signals that are active during input acquisition, contribute noise to the conversion result. If the noise signal is synchronous to the sampling interval, an effective input offset is produced. Asynchronous signals produce random noise on the input, whose high-frequency components may be aliased into the frequency band of interest. Minimize noise by presenting a low impedance (at the frequencies contained in the noise signal) at the inputs. This requires bypassing AIN to AGND, or buffering the input with an amplifier that has a small-signal bandwidth of several MHz, or preferably both. AIN has a bandwidth of about 4MHz.
0.1F 2 7 6
1000pF
AIN IN 3
MAX427
4 0.1F -15V
20
0.0033F
Figure 8. AIN Buffer for AC/DC Use
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14-Bit ADC, 200ksps, +5V Single-Supply with Reference MAX1142/MAX1143
Offsets resulting from synchronous noise (such as the conversion clock) are canceled by the MAX1142/ MAX1143's calibration scheme. The magnitude of the offset produced by a synchronous signal depends on the signal's shape. Recalibration may be appropriate if the shape or relative timing of the clock or other digital signals change, as might occur if more than one clock signal or frequency is used. which it will be used to do conversions. The part will remain in calibration mode for approximately 80,000 clock cycles, unless the calibration is aborted. Calibration is halted if RST or SHDN goes low, or if a valid start condition occurs.
Distortion Avoid degrading dynamic performance by choosing an amplifier with distortion much less than the MAX1142/ MAX1143's THD (-88dB) at frequencies of interest. If the chosen amplifier has insufficient common-mode rejection, which results in degraded THD performance, use the inverting configuration to eliminate errors from common-mode voltage. Low temperature-coefficient resistors reduce linearity errors caused by resistance changes due to self-heating. To reduce linearity errors due to finite amplifier gain, use an amplifier circuit with sufficient loop gain at the frequencies of interest. DC Accuracy If DC accuracy is important, choose a buffer with an offset much less than the MAX1142/MAX1143's maximum offset (6mV), or whose offset can be trimmed while maintaining good stability over the required temperature range.
Software Shut-Down A software power-down is initiated by setting M1 = 1, M0 = 0. After the conversion completes, the part shuts down. It reawakens upon receiving a new start bit. Conversions initiated with M1 = 1 and M0 = 0 (shutdown) use the acquisition mode selected for the previous conversion.
Shutdown Mode
The MAX1142/MAX1143 may be shut down by pulling SHDN low or by asserting software shutdown. In addition to lowering power dissipation to 13W, considerable power can be saved by shutting down the converter for short periods between conversions. Duration will be affected by REF startup time with internal reference. There is no need to perform a calibration after the converter has been shut down, unless the time in shutdown is long enough that the supply voltage or ambient temperature may have changed.
Supplies, Layout, Grounding and Bypassing
For best system performance, use separate analog and digital ground planes. The two ground planes should be tied together at the MAX1142/MAX1143. Use pins 3 and 14 as the primary AGND and DGND, respectively. If the analog and digital supplies come from the same source, isolate the digital supply from the analog with a low value resistor (10). The MAX1142/MAX1143 are not sensitive to the order of AVDD and DVDD sequencing. Either supply can be present in the absence of the other. Do not apply an external reference voltage until after both AVDD and DVDD are present. Be sure that digital return currents do not pass through the analog ground. All return current paths must be low-impedance. A 5mA current flowing through a PC board ground trace impedance of only 0.05, creates an error voltage of about 250V, or about 2LSBs error with a 4V full-scale system. The board layout should ensure that the digital and analog signal lines are kept separate. Do not run analog and digital lines parallel to one another. If you must cross one with the other, do so at right angles. The ADC is sensitive to high-frequency noise on the AVDD power supply. Bypass this supply to the analog ground plane with 0.1F. If the main supply is not ade-
Operating Modes and Serial Interfaces
The MAX1142/MAX1143 are fully compatible with MICROWIRE and SPI/QSPI devices. MICROWIRE and SPI/QSPI both transmit a byte and receive a byte at the same time. The simple software interface requires only three 8-bit transfers to perform a conversion, one 8-bit transfer to configure the ADC, and two more 8-bit transfers to clock out the 14-bit conversion result.
Mode 1 Short Acquisition Mode (24 SCLK) Configure short acquisition by setting M1 = 0 and M0 = 0. In short acquisition mode, the acquisition time is 5.5 clock cycles. The total period is 24-clock cycles per conversion. Mode 2 Long Acquisition Mode (32 SCLK) Configure long acquisition by setting M1 = 1 and M0 = 1. In long acquisition mode, the acquisition time is 13.5 clock cycles. The total period is 32 clock cycles per conversion. Calibration Mode A calibration is initiated through the serial interface by setting M1 = 0, M0 = 1. Calibration can be done in either internal or external clock mode, though it is desirable that the part be calibrated in the same mode in
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14-Bit ADC, 200ksps, +5V Single-Supply with Reference
quately bypassed, add an additional 1F or 10F lowESR capacitor in parallel with the primary bypass capacitor.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight-line can be either a best straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. INL for the MAX1142/MAX1143 is measured using the endpoint method.
MAX1142/MAX1143
Transfer Function
Figures 10 and 11 show the MAX1142/MAX1143's transfer functions. In unipolar mode, the output data is in binary format and in bipolar mode, it is two's complement format.
OUTPUT CODE FULL-SCALE TRANSITION
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1LSB. A DNL error specification of less than 1LSB guarantees no missing codes and a monotonic transfer function.
11 . . . 111 11 . . . 110 11 . . . 101
Aperture Jitter
FS = +4.096V 1LSB = FS 16384
Aperture jitter (tAJ) is the sample-to-sample variation in the time between the samples.
Aperture Delay
Aperture delay (t AD ) is the time between the rising edge of the sampling clock and the instant when an actual sample is taken.
00 . . . 011 00 . . . 010 00 . . . 001 00 . . . 000 0 1 2 3 FS - 3/2LSB FS
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (SNR) is the ratio of fullscale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical, minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC's resolution (N-bits): SNR = (6.02 ! N + 1.76)dB In reality, there are other noise sources besides quantization noise, including thermal noise, reference noise, clock jitter, etc. Therefore, SNR is calculated by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics and the DC offset.
INPUT VOLTAGE (LSBs)
Figure 10. MAX1143 Unipolar Transfer Function, 4.096V = FullScale
OUTPUT CODE
+FS = +4.096V 011 . . . 111 011 . . . 110 1LSB = 8.192 16384 -FS = -4.096V
000 . . . 010 000 . . . 001 000 . . . 000 111 . . . 111 111 . . . 110 111 . . . 101
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequency's RMS amplitude to the RMS equivalent of all other ADC output signals: SINAD (dB) = 20 ! log (SignalRMS/NoiseRMS)
100 . . . 001 100 . . . 000 -FS 0V INPUT VOLTAGE (LSBs) +FS - 1LSB
Figure 11. MAX1143 Bipolar Transfer Function, 4.096V = FullScale
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14-Bit ADC, 200ksps, +5V Single-Supply with Reference MAX1142/MAX1143
Effective Number of Bits
Effective number of bits (ENOB) indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC's error consists of quantization noise only. With an input range equal to the fullscale range of the ADC, calculate the effective number of bits as follows: ENOB = (SINAD - 1.76) / 6.02
Typical Application Circuit
+5V
0.1F AVDD SHDN +5V 0.1F
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as: THD = 20 x log V2 2 + V3 2 + V4 2 + V5 2 / V1 where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics.
1F 2.2F 0.22F AIN
MAX1142 MAX1143
DVDD
TO DGND CS SCLK DIN DOUT RST SSTRB
CREF REF REFADJ
MC68HCXX I/O SCLK MOSI MISO I/O
DGND AGND
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS amplitude of the fundamental (maximum signal component), to the RMS value of the next largest distortion component.
Ordering Information (continued)
PART MAX1142AEAP TEMP. RANGE -40C to +85C -40C to +85C 0C to +70C 0C to +70C -40C to +85C -40C to +85C PINPACKAGE 20 SSOP 20 SSOP 20 SSOP 20 SSOP 20 SSOP 20 SSOP INL (LSB) 1 2 1 2 1 2
Chip Information
TRANSISTOR COUNT: 21,807 PROCESS : BiCMOS
MAX1142BEAP MAX1143ACAP* MAX1143BCAP* MAX1143AEAP* MAX1143BEAP*
*Future product--contact factory for availability.
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14-Bit ADC, 200ksps, +5V Single-Supply with Reference
Functional Diagram
MAX1142/MAX1143
AVDD AGND CREF REFADJ REF AIN INPUT SCALING NETWORK DAC COMPARATOR REFERENCE 9k
MAX1142 MAX1143
ANALOG TIMING CONTROL
DVDD DGND CS SCLK DIN RST SHDN SERIAL INPUT PORT CLOCK GENERATOR MEMORY CALIBRATION ENGINE SERIAL OUTPUT PORT SSTRB DOUT P2 P1 P0 CONTROL
______________________________________________________________________________________
19
14-Bit ADC, 200ksps, +5V Single-Supply with Reference MAX1142/MAX1143
Package Information
SSOP.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
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